Basics of Superscalar Processor

Superscalar Processors are generally studied as an extension to an in-order Pipelined Processor.
Let's start with a simple analogy for simple understanding of the overall structure of the processor.
Consider an instruction as a car on a highway. Highway, here, is analogous to the processor. Now, an in-order pipelined processor can be thought as single lane on which only a single car can pass per unit time.
Technically, therefore we can achieve a maximum IPC (instructions per cycle) of 1(unity).
Intuitively, the solution to this would be to increase the number of lanes of the highway. This my friend is the simplest possible image of a superscalar type of architecture.

The first question that comes to mind is how exactly is this possible? Most of the instructions that we run are dependent on each other. So, how exactly can we run multiple instructions in parallel?
Let's take on each question one by one.

1. A superscalar processor is full of subtleties. How to make it possible exactly will be coming up in following blogs.
2. As opposite to the general intuition that most of the instructions are inter-dependent, there is a lot of independence among blocks of code. We can take advantage of this independence with the help of a compiler (VLIW processor) or with (up to some extent) a superscalar processor.

Generally instructions in a superscalar processor are executed out-of-order. What this means is:

• If the input instructions are in the following order:
1. ADD R1, R2, R3
2. SUB R4, R5, R6
• The actual order of the execution can be instruction 2 followed by instruction 1

Note: The two instructions taken in the example are independent. Also, out-of-order execution is not always possible.