Structure A typical entry in the reorder buffer can be visualized as: Busy Instruction Type Validity Register Affected Data 1 bit 2 bit 1 bit 3 bit 16 bits The values shown above are in accordance with the designed mini-superscalar processor. Whenever an instruction is decoded, an entry is allotted to it in the reorder buffer. Index corresponding to this is returned to the corresponding instruction. The busy bit is set to '1' whenever an entry is allotted to an instruction and is cleared to '0' whenever the instruction is declared as completed. Completion : An instruction is changed to be completed when all of its preceding instructions are completed. To manage this, a register (R_old) is defined which holds the index value to the oldest instruction. If the validity of this is set to '1' by the execute stage, this instruction is...

Data Dependencies While executing instructions it is quite possible that an instruction reads a value that the previous instruction changes.  In a pipeline, the first instruction thus, has to wait until the previous instruction finishes it's execution.This dependence of data of an instruction on it's previous instruction is referred to as data dependency. Data dependencies are of two types: True Data Dependency False Data Dependency Let us now consider each of it with an example. True Data Dependency Consider the following example: 1.  a = b + c 2. d = a  + e Instruction 2 depends on 'a'  before it can start executing. Therefore instruction 1 must complete it's execution before instruction 2 can start. This is an example of true data dependency. Herein the input operands of one instruction directly depends on the output operands of the instruction(s) before or after it. Thus this is further divided into two: (1) Read after Write ( RAW ) (a...